This invention relates to data memories, and more particularly, relates to circuitry and method for providing input and output buffering for a memory cell by using integrated injection logic (I.sup.2 L).
An I.sup.2 L memory cell was disclosed in an article by S. K. Wiedmann appearing in IEEE Journal of Solid State Circuits in October, 1973 on page 332. When many such cells are used in a memory it becomes necessary to provide some isolation or buffering between cells, otherwise, data appearing on the input terminal may very well disturb contents of other cells within the memory. Also output buffering must be provided or other cells in the memory may interfere with proper reading of a desired cell. A resistor or a diode in series with the input gate of the memory cell and the data input line could be used to provide the desired buffering. However, since many I.sup.2 L memory cells plus other interface circuitry and registers can all be manufactured on a single integrated circuit chip it becomes overly costly in the amount of chip area consumed just to separately isolate the resistors or the diodes on the semiconductor chip. In addition, since the resistors must be large in ohmic value to adequately isolate the cells they would require a relatively large area of the semiconductor chip.
In view of the foregoing, it should now be understood that it would be desirable to provide an improved isolation scheme for the memory cell that would solve the above and other problems.
Accordingly, one of the objects of the present invention is to provide an improved memory cell that will not cause nor suffer from current hogging effects with adjacent cells.
Another object of the invention is to provide a memory having cells that are adequately buffered so that noise on an output data line does not change the information stored in the cell.
A further object of the invention is to provide an improved memory wherein each cell of the memory is essentially buffered by at least two gates.
Yet another object of the present invention is to provide an improved memory using I.sup.2 L circuitry and requiring a reduced die size since one metal line can be used to go to the inputs of all the individual cells of the memory.